62
8008H–AVR–04/11
ATtiny48/88
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven
high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port
pin is driven low (zero).
10.2.2
Toggling the Pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Note that the SBI instruction can be used to toggle one single bit in a port.
10.2.3
Break-Before-Make Switching
In the Break-Before-Make mode when switching the DDRxn bit from input to output an immedi-
ate tri-state period lasting one system clock cycle is introduced as indicated in Figure 10-3. For
example, if the system clock is 4 MHz and the DDRxn is written to make an output, the immedi-
ate tri-state period of 250 ns is introduced, before the value of PORTxn is seen on the port pin.
To avoid glitches it is recommended that the maximum DDRxn toggle frequency is two system
clock cycles. The Break-Before-Make is a port-wise mode and it is activated by the port-wise
BBMx enable bits. For details on BBMx bits, see “PORTCR – Port Control Register” on page 77.
When switching the DDRxn bit from output to input there is no immediate tri-state period
introduced.
Figure 10-3. Break Before Make, switching between input and output
10.2.4
Switching Between Input and Output
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output
low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-
able, as a high-impedant environment will not notice the difference between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all
pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}
= 0b11) as an intermediate step.
out DDRx, r16
nop
0x02
0x01
SYSTEM CLK
INSTRUCTIONS
DDRx
intermediate tri-state cycle
out DDRx, r17
0x55
PORTx
0x01
intermediate tri-state cycle
Px0
Px1
tri-state
0x01
R17
0x02
R16
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